TSMC targets 5nm volume production in 2020, 80% higher transistor density compared to 7nm

Written by Neil Soutter on Sun, May 5, 2019 12:00 PM

Taiwanese semiconductor manufacturer TSMC has published its Q1 2019 financial results, taking the opportunity to talk about its upcoming 5nm fabrication plans.

The very first 7nm graphics card arrived earlier this year in the form of the Radeon VII, while both AMD’s 7nm Zen 2-powered Ryzen 3000 series and Navi GPUs are due to launch in Q3 2019. TSMC is already forging well ahead with its 6nm and 5nm plans, leaving the likes of Intel floundering on its well-publicized 10nm fabrication issues.

"N5 [5nm] technology development is well on track," TSMC chairman and CEO C.C. Wei said on TSMC’s Q1 earnings call. “With the best density performance, power, and the best transistor technology, we expect most of our customers who are using 7nm today will adopt 5nm.”

In terms of the here and now, 7nm is still the big focus. A large number of TSMC’s clients are taping out 7nm products across a wide range of industries. Volume production is already in full flow for 7nm+, which utilises EUV (Extreme Ultra Violet lithography). 7nm+ yields have now matched 7nm, and TSMC believes around 25% of its total revenue will come from 7nm wafers.

Both the 6nm and 5nm fabrication nodes are deep into development though, with 5nm offering 1.8x the transistor density of 7nm. “The number N6 and N5 looks pretty close. but actually they still have a big gap,” said Wei, demonstrating his knowledge of the numeric system. “N5 compared with N7, actually, the logic density increases by 80%. N6 compared with N7 is only 18%. So you can see there’s a big difference in that logic density and transistor performance also. And so, as a result, the total power consumption in the chip is lower in the N5. There’s a lot of benefit if you move into N5.”

If all that’s got your head in a whirl, it just means hardware manufacturers can use smaller transistors in order to cram in more on the same size chip. TSMC believes hardware manufactures will be using 5nm for the long haul. Clients need time to catch up with the advances in fabrication, and N5 should offer a suitable impressive performance and power efficiency advantage over 7nm. TSMC is currently on target for the volume production of 5nm wafers in the first half of 2020.

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23:43 May-05-2019

I wonder when graphite would be used.

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05:58 May-06-2019

My guess, in 10 - 20 years.

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08:50 May-06-2019

Graphite is taking a really long time to be used. Mostly because its expensive and its still in research. Ever since the 90s oof

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10:36 May-06-2019

It is in use tho not to the extend that it was hyped up to be.


I know this videos is from Verge but it's an ok description of the graphite situation.


Link

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21:45 May-06-2019

I've seen it. Still interested in where it could be used at.

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12:24 May-07-2019

One application that was mentioned were batteries, among other things.


Time will tell...

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00:45 May-08-2019

Goddammit its gonna take a long time

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18:39 May-10-2019

Progress rarely happens at the pace we want.

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19:25 May-05-2019

And why intel is having a hard time going below 14nm?

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19:35 May-05-2019

That's something only Intel currently knows.

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20:00 May-05-2019

i believe its got something to do that intels litography is more dense than competition? I dont know, just i remember something like that maybe im mistaken with global foundries litography compared to tsmc?

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20:46 May-05-2019

@Therione13
Because they are stubborn, as they should be, they want to have the best process node as they have had since... well about the 90s or so, so basically since forver.
If they make their so called 10nm process node up to target spec, it will be faster and more power efficient than TSMC's 7nm and denser and smaller than 7nm too... so yeah... Of course the high thermal desnity might cause heat problems, but that's nothing new for their chips.

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07:44 May-06-2019

Yep. Even when that node was being trouble for over half a decade and their competitor they've been leaving in the dust is now back wiping their ass with them. Even amidst all the shortages and reported financial issues too.

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07:45 May-06-2019

Sometimes you gotta concede defeat and move on so you can actually afford to fight another day. That being said, I wish them the best as long as AMD are doing their best too.

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09:44 May-06-2019

The node is two years behind planned, so it's not in trouble for half a decade, but still they should go for it, it's probably the last division of intel that is not milking us.
And on top of that it's absolutely guaranteed they are developing the node after 10nm parallel to 10nm, so don't worry. Do you think TSMC started working on 5nm after 7nm was finished? Nah. Of course the latter is most likely a lower priority until it becomes current, but still.

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11:03 May-06-2019

In 2014 Intel started full time work on their 10nm node and planned to have chips in full production in 2016. That was later delayed to now presumably early 2020, which is well over 4 years of trouble + what they've already been working.

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14:46 May-06-2019

Wait, didn't they announce a 3x year cycle in 2014 with the Devil Canyon refresh of Haswell? Thus a 3x year gap between a process node?

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14:24 May-05-2019

cries in intel

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12:56 May-05-2019

pffff nice joke

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13:46 May-05-2019

it's not a joke.

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15:45 May-05-2019

That's not a joke... TSMC finished their design for 5nm and it has entered into testing phase.

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12:47 May-05-2019

Would be interesting to see how small they can go before adopting new techniques of creating chips

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12:57 May-05-2019

how much FPS you got in PUBG?

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13:27 May-05-2019

I don't play PUBG :(

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13:48 May-05-2019

@Mithu612 well considering that they've got a dozen more process nodes to go before they become too small, there is time to see.

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19:12 May-05-2019

Which dozen more? Even IBM, the world leading power in semiconductors and usually first to shrink nodes is having incredible trouble developing the so called 3nm node and they're not certain it could even work on Silicon anymore.

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19:12 May-05-2019

So unless you know something that those engineers don't, you're not really correct.

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19:20 May-05-2019

Yeah they said the same thing about 90nm and how hard it would be to go below 100nm, then 65nm, then 45/40nm, then 12-16nm, then 10/7nm... I would be surprised if they for once said it's a piece of cake :D

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19:29 May-05-2019

Yes, but for that the biggest problem was the technology used to achieve it. I've read somewhere that physical properties of Silicon at such low, low scale play some serious problems with the flow of electricity...

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19:29 May-05-2019

... which is why they believe that lower can't go. It is possible that they could develop a new piece of tech to help them, but as of right now such a thing doesn't exist.

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20:50 May-05-2019

It's not with the flow of electricity, it's with the leakage of voltage and electricity, meaning that it would have to consume more power or it will crash(crash means be permenantly on).


Intel had the exact same problem with 45nm, so they introduced an aditional barrier layer or whatever they called and badabing badabong it worked, what took the most time was to change their equipment to be able to produce it.

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09:43 May-06-2019

Leaking voltage means the flow is incorrect. The main line is correct but any leaks means the flow has problems.

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11:06 May-06-2019

He has a knack for always "outsmarting" and one upping people mostly to his own detriment. He desperately want to sound smarter than those he talks to and I'm stupid enough to let him do so.

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14:57 May-06-2019

There are many types of leakages, the most common is either a source or a drain leakage(depending on PNP or NPN), which means that even if the transistor is off(switch state off), a small current still passes through, that is no biggie with normal sized transistors, but it scales proportionally up the smaller the process node becomes, and at some point the current that still passes through the transistor becomes big enough that regardless if the transistor is on or off(thinking of them as switches) the passing current is high enough to switch the next transistors in the pipeline, this is caused by the voltage being too high for the drain/source, the current is just the effect, the voltage is the cause, thus you need the next transistor on the pipeline to consume more and more power.

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15:00 May-06-2019

Steve, you alone can make my day. You are always there to oppose everything I say and I love it, it's the debater's dream come true, I don't care what your reasoning behind it is, it's purely fantastic and entertaining, and I love how you see bad meanings(if not the worst) in everything I say, when I don't state them, nor imply them at all. You should have joined GD earlier.

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19:12 May-06-2019

If the electricity changes it's own path as you pointed out, that would be leakage.
Leakage -
PHYSICS
the gradual escape of an electric charge or current, or magnetic flux.

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20:55 May-06-2019

Then how was having a higher voltage than the threshhold called, which causes the current "leakage"? O_o

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15:46 May-07-2019

Ok...what? Your comment makes no grammatical sense.
Since you want to argue, I'll bring in a higher power and you can take it up with them. I pasted their definition but here's the link.
https://en.oxforddictionaries.com/definition/leakage

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16:02 May-07-2019

I didn't argue I asked a question.

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17:24 May-07-2019

read your comment then because i think you typed in the wrong word. its really confusing to read.

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12:46 May-05-2019

Wasn't 7nm supposed to be the smallest we can possibly go? If not then what is?

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12:58 May-05-2019

7nm was believed to be the smallest we could possibly go without problems, which has been changed to 5nm, and even possibly, but unlikely, 3nm node, but that's most probably the actual final point to as far as it could go on silicon.

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13:49 May-05-2019

well if it was really 7nm sure, but it's not...
14nm is not 14nm either, a "14nm" transistor has an area of 5760nm, so yeah... nothing is 7nm or 5nm or 3nm or 14nm about any of those process nodes, it's been a marketing shtick for years now.

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15:59 May-05-2019

This guy is like those car nuts. You ask the dude what car that is and he breaks down a full list of specifications and clarifications for every single moving part of the vehicle, even though you've asked a very simple question.

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16:00 May-05-2019

They all do this just to prove how smart they are, even though the answer they give is completely detached from the question they were asked and thus the only thing they end up being is just extremely annoying.

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18:35 May-05-2019

Well that's the thing, I clarified. He clearly thinks that the 7nm process node is around 7nm in size, when in reality it is not.

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19:02 May-05-2019

Where'd you get that from? He never said that he thinks 7nm node is 7nm. Everyone using the name in the tech space probably already knows that name is only for branding and not representative of the actual size of the transistors.

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19:04 May-05-2019

You clarified a question that was never asked and you've not even answered his question in the end. You just decided to play smart to play smart.

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19:07 May-05-2019

I thought the amount of nm referred to the distance between each transistor and not the area of the transistor itself?

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19:16 May-05-2019

@Assassins102 They used to, but at some point they have fallen off and decided to stick to the already branding for marketing purposes and familiarity. Some have proposed that we should count transistor density for each node...

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19:19 May-05-2019

But that didn't take hold. As it stands today it's just mostly a marketing term. That being said, what is now called 5nm is still considered the possible lowest point on Silicon.

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19:19 May-05-2019

IBM could probably finagle the 3nm node, but considering the trouble they're having with it, it's possible that if they ever do, they probably won't be going further on Silicon at least.

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19:31 May-05-2019

If we do wanna go completely off the rails. You are to a part correct. 7nm on a "7nm" transistor refers to the smallest spacing between repeated features on a chip along a certain direction.

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19:34 May-05-2019

Transistors consist of fin shaped pieces of silicon, each fin the "xx nm" wide and a lot more nm long and tall. That is the "7nm" in 7 nm chips.

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20:59 May-05-2019

Because he said we can't go smaller than that, when we can.
Also 7nm's fins are speced at 30nm well global foundry's 7nm anyway(which I think got canceled)... so again nothing about it is 7nm, I can't find a single spec that is any of the namesake nanometers...
https://imgur.com/a/Zn2OuRS
check specs first mate, or if you can find more detailed specs, I'd be very thankful, cuz I coudln't.


I think intel's 10nm's spec had a fin width of 8nm btw, but it could have been 18nm... I forgot... still nothing is 10nm about it... and still it's just targeted specs.

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16:53 May-05-2019

Well, I remember about 20 years ago everyone said HDDs will not be bigger than 40GB... :D
What I'm trying to say, predictions are sometimes not that accurate :)

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18:48 May-05-2019

Not really on topic, but I remember my first "IBM Compatible" computer as PCs were called back in the day. It was advertised to have all the storage you would ever need. A whopping 128 MB of storage.

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19:05 May-05-2019

Those good old days.

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20:10 May-05-2019

If I can just get a yottabyte SSD with 5 exabit read and write speed, I'll be good at least for a while.

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12:44 May-05-2019

and thus we reach the minimum size of conventional transistors

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13:51 May-05-2019

around 2016-3072nm? nah, we should be able to go smaller than that.

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19:40 May-05-2019

"At the 45 nm process, Intel reached a gate length of 25 nm on a traditional planar transistor. At that node the gate length scaling effectively stalled; any further scaling to the gate length would produce less desirable results. Following the 32 nm process node, while other aspects of the transistor shrunk, the gate length was actually increased."

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19:41 May-05-2019

"With the introduction of FinFET by Intel in their 22 nm process, the transistor density continued to increase all while the gate length remained more or less a constant. This is due to the properties of FinFET; for example the effective channel length is a function of the new fins (Weff = 2 * Hfin + Wfin). Due to how the transistor changed dramatically from how it used to be, the current naming scheme lost any meaning."

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22:05 May-05-2019

yeah basically, naming has lost all it's meaning for a decade now... -_-

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